Many ICs have stringent operating requirements, and are required to operate over a variety of conditions, such as varying voltage/current levels/timing and ambient temperatures. The testing procedures for complex ICs, such as field-programmable gate arrays (“FPGAs”), application-specific integrated circuits (“ASICs”), microprocessors, and memories can be very time consuming and represent a significant portion of the total manufacturing time and cost.
Non-room temperature testing is particularly expensive because it uses hot or cold test fixtures, which are relatively expensive compared to room temperature (“RT”) test fixtures, and the device under test must be brought to the appropriate temperature, which adds time into the test sequence. Testing a device at a temperature hotter than room temperature can be twice as costly, and testing a device at a temperature colder than room temperature can be four to six times as costly.
Many approaches have been tried to meet quality requirements over a wide range of temperatures for ICs. Testing each IC at both ends of the devices' specified temperature operating range is direct, time consuming, and expensive, but acceptable for some devices, such as low-volume specialty devices. Other devices are 100% tested at room temperature and high temperature, but are only sampled for testing at cold temperature. Unfortunately, sampling cannot assure the required quality for all IC products, and price constraints often preclude 100% cold testing of high-volume parts.
Techniques have been developed to associate cold (or hot) IC failures with single temperature (typically RT) electrical measurements. One technique varies the external electrical test conditions, such as varying an external test voltage, to simulate or mimic low or high temperature operation. Other techniques use test guard bands (i.e., more stringent RT test limits, also called parametric modification), sometimes in conjunction with varied electronic test conditions, to identify ICs that have a propensity for failure at the maximum or minimum operating temperature based on statistical characterization of the IC and the test conditions. However, parametric modification of external test conditions is not able to identify all possible low-temperature failures.
Techniques for detecting defects in ICs that manifest at cold or hot temperatures using RT electrical testing that avoids the limitations of the prior art are desired.